Building Registers
Registers make up around a quarter of my processor area. They are just small memory holders which you access not by address but by some other signal.
In this blog post, we will explore why registers are essential, their role in digital circuits, and how they are constructed. We will later explain why we need so many of them.
Why Do We Need Registers?
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Multiple Values: Memory is an indispensable part of digital systems, but it's not enough on its own. Sometimes, we need to access and manipulate multiple values simultaneously. For instance, when fetching data from memory, we require the memory address as an input.
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Arithmetic Operations: Many arithmetic operations, like addition or NAND, involve two operands. Registers are crucial because they allow us to store and manipulate these operands before and after operations.
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Temporary Outputs: Digital systems often perform complex operations that don't yield an instant result. Instead, intermediate values are computed and stored temporarily. Registers serve as these temporary storage locations, ensuring data consistency.
This list is not exhaustive, but you get the point, we need them.
Building a Register
Register is just something that stores some state or number. That thing that we construct should have:
- some input that it will remember
- enable in signal (when it is 1 register will remember the input)
- output signal
- enable out signal (when it is 1 register should output the state to the bus)
1. State Holding with Not Gates
Let's start by exploring a basic concept: state holding. Registers need to retain information over time. One simple way to achieve this is by connecting two NOT gates in a loop. This setup can hold a state, but it lacks the ability to input or output data.
2. The SR Latch
To create a register that can store data and allow for input and output, we can turn to the SR latch. SR stands for Set-Reset, and it uses two NOR or two NAND gates. Below is the truth table for an SR latch:
| ¬S | ¬R | Q | ¬Q |
|---|---|---|---|
| 0 | 0 | Prev (Q) | Prev (¬Q) |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | X | X |
The SR latch has two inputs, S (Set) and R (Reset), and two outputs, Q and ¬Q. It can store one bit of information. We can construct it by looping two NAND gates:
3. The Gated SR Latch
To make the SR latch more versatile, we can add an "enable" input that controls when data can be written to the latch. This is known as a Gated SR latch. When the enable line is set to 1, data can be written ; when it's set to 0, no changes occur. Below is the truth table for a Gated SR latch:
| E | ¬S | ¬R | Q | ¬Q |
|---|---|---|---|---|
| 0 | X | X | Prev (Q) | Prev (¬Q) |
| 1 | 0 | 0 | Prev (Q) | Prev (¬Q) |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | X | X |
The Gated SR latch offers more control over the state transitions and allows data to be stored or retrieved as needed.
4. The D Latch: Simplicity and Functionality
The D latch, also known as the Data or Transparent latch has a single data input (D) and one control input Enable (E). Comparing it to the gated SR latch we can see that it does not need two inputs, it "creates" the inverse input.
| E (Enable) | D (Data Input) | Q (Output) |
|---|---|---|
| 0 | X | Prev (Q) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The E input controls whether the latch is transparent (E = 1) or locked (E = 0). When E = 1, the D latch allows data to flow from D to Q. It is easy to create the D latch with our current knowledge. We need to add 4 NAND gates and one NOT. We contruct the Gated SR latch and use the NOT gate to create S and R from D:
The interesting thing is that we can do better, we can completely remove the NOT gate. One property
of the NAND gate is:
NAND( NAND(A, B), B) = NAND(NOT A, B)
You can write the full truth table, but it is easier to reason why. If B==1 we can just delete
it, than NAND(A,1) == NOT A and the idendity holds. If B==0 both left and right is 1. If we look at
our constructed latch we have the right part (nand1) and we can easily reuse nand0 to make the left
part and remove one NOT gate.
We can than chain them to store multiple bits.
4. Gated D Latch: final circuit
To connect the output of the register to the bus we need to gate the output as explained in a previous post (if something does not output to the bus it should pullup the bus). Luckily we don't need to negate the noutput of the latch because we already have the output. This is than the final register circuit:
To store 8 bits of data we just put 8 of these register cells we created.
Timing Characteristics: Setup Time and Hold Time
The exact numbers regarding these timings are not of interest to us, it is just important to acknowledge their existance. Two essential timing parameters are setup time and hold time. These two numbers as well as metastability are part of the core understanding. Check the edge triggered chapter for more info.